Computer Architecture-OBJECTIVE TYPE 75 QUESTIONS-Gate

Computer Architecture-OBJECTIVE TYPE 75 QUESTIONS-Gate

 Computer Architecture

PART - I

OBJECTIVE TYPE QUESTIONS

Choose correct or the best alternative in the following:

Q.1 In a virtual memory system, the addresses used by the programmer belongs to

(A) memory space. (B) physical addresses.

(C) address space. (D) main memory address.

Ans: C

An address used by programmers in a system supporting virtual memory concept is

called virtual address and the set of such addresses are called address space.

Q.2 The method for updating the main memory as soon as a word is removed from the

Cache is called

(A) Write-through (B) write-back

(C) protected write (D) cache-write

Ans: B

In this method only cache location is updated during write operation.

Q.3 A control character is sent at the beginning as well as at the end of each block in the

synchronous-transmission in order to

(A) Synchronize the clock of transmitter and receiver.

(B) Supply information needed to separate the incoming bits into individual

character.

(C) Detect the error in transmission and received system.

(D) Both (A) and (C).

Ans B

As the data are sent continuously as a block of data at the rate dictated by the clock

frequency, so the receiver should be supplied with the same function about the same

bit length in order to interrupt the information.

Q.4 In a non-vectored interrupt, the address of interrupt service routine is

(A) Obtained from interrupt address table.

(B) Supplied by the interrupting I/O device.

(C) Obtained through Vector address generator device.

(D) Assigned to a fixed memory location.

Ans: D

The source device that interrupted the processor supply the vector address which

helps processor to find out the actual memory location where ISR is stored for the

device.

Q.5 Divide overflow is generated when

(A) Sign of the dividend is different from that of divisor.

(B) Sign of the dividend is same as that of divisor.

(C) The first part of the dividend is smaller than the divisor.

Ans: B

If the first part of the dividend is greater than the deviser, then the result should be

of greater length, then that can be hold in a register of the system. The registers are

of fixed length in

any processor.

Q.6 Which method is used for resolving data dependency conflict by the compiler

itself?

(A) Delayed load. (B) operand forwarding.

(C) Pre fetch target instruction. (D) loop buffer.

Ans: A

In case of delayed load technique the complier detects the data conflict and reorder

the instruction as necessary to delay the loading of the conflicting data by inserting

no operation instructions.

Q.7 Stack overflow causes

(A) Hardware interrupt.

(B) External interrupt.

(C) Internal interrupt.

(D) Software interrupt.

Ans: C

Stack overflow occurs while execution of a program due to logical faults. So it is a

program dependent, hence interrupt activated.

Q.8 Arithmetic shift left operation

(A) Produces the same result as obtained with logical shift left operation.

(B) Causes the sign bit to remain always unchanged.

(C) Needs additional hardware to preserve the sign bit.

(D) Is not applicable for signed 2's complement representation.

Ans: A

If the register hold minus five in two’s compliment form than in arithmetic shift left

the contents of the register shall be

It is found that the register contents multiplied by two after logical shift left

operation. Hence arithmetic shift left operation is same as logical shift operation.

Q.9 Zero address instruction format is used for

(A) RISC architecture.

(B) CISC architecture.

(C) Von-Neuman architecture.

(D) Stack-organized architecture.

Ans: D

In stack organized architecture push and pop instruction is needs a address field to

specify the location of data for pushing into the stack and destination location

during pop operation but for logic and arithmetic operation the instruction does not

need any address field as it operates on the top two data available in the stack.

Q.10 Address symbol table is generated by the

(A) memory management software.

(B) assembler.

(C) match logic of associative memory.

(D) generated by operating system

Ans: B

During the first pass of assembler address symbol table is generated which contains

the label used by the programmer and its actual address with reference to the stored

program.

Q.11 The ASCII code for letter A is

(A) 1100011 (B) 1000001

(C) 1111111 (D) 0010011

Ans. (B)

Q.12 The simplified expression of (A+B) + C is

(A) (A + B)C (B) A(B + C)

(C) (C+A + B) (D) None of these

Ans. (A)

Q.13 The negative numbers in the binary system can be represented by

(A) Sign magnitude (B) I's complement

(C) 2's complement (D) All of the above

Ans. (C)

Q.14 ABCD - seven segment decoder / driver in connected to an LED display.

Which segments are illuminated for the input code DCBA = 0001.

(A)b, c (B) c, b

(C)a, b, c (D) a, b, c, d

Ans. (A)

Q.15 How many flip-flops are required to produce a divide-by-32 device?

(A)4 (B) 6

(C)5 (D) 7

Ans. (C)

Q.16 The content of a 4-bit register is initially 1101. The register is shifted 2 times to

the right with the serial input being 1011101.

What is the content of the register after each shift?

(A)1110, 0111 (B) 0001, 1000

(C)1101, 1011 (D) 1001, 1001

Ans. (A)

Q.17 How many different addresses are required by the memory that contain 16K

words?

(A)16,380 (B) 16,382

(C)16,384 (D) 16,386

Ans. (C)

Q.18 What is the bit storage capacity of a ROM with a 512' 4-organization?

(A) 2049 (B) 2048

(C) 2047 (D) 2046

Ans. (B)

Q.19 DMA interface unit eliminates the need to use CPU registers to transfer data

from

(A) MAR to MBR (B) MBR to MAR

(C) I/O units to memory (D) Memory to I/O units

Ans. (D)

Q.20 How many 128 x 8 RAM chips are needed to provide a memory capacity of

2048 bytes?

(A) 8 (B) 16

(C) 24 (D) 32

Ans. (B)

Q.21 Which of the following is a self complementing code?

(A) 8421 code (B) 5211

(C) Gray code (D) Binary code

Ans. (A)

Q.22 Which gate can be used as anti-coincidence detector?

(A) X-NOR (B) NAND

(C) X-OR (D) NOR

Ans. (C)

Q.23 Which of the following technology can give high speed RAM?

(A) TTL (B) CMOS

(C) ECL (D) NMOS

Ans. (C)

Q.24 In 8085 microprocessor how many I/O devices can be interfaced in I/O mapped

I/O technique?

(A) Either 256 input devices or 256 output devices.

(B) 256 I/O devices.

(C) 256 input devices & 256 output devices.

(D) 512 input-output devices.

Ans. (C)

Q.25 After reset, CPU begins execution of instruction from memory address

(A) 0101H (B) 8000H

(C) 0000H (D) FFFFH

Ans. (C)

Q.26 Which is true for a typical RISC architecture?

(A) Micro programmed control unit.

(B) Instruction takes multiple clock cycles.

(C) Have few registers in CPU.

(D) Emphasis on optimizing instruction pipelines.

Ans. (A)

Q.27 When an instruction is read from the memory, it is called

(A) Memory Read cycle (B) Fetch cycle

(C) Instruction cycle (D) Memory write cycle

Ans. (B)

Q.28 Which activity does not take place during execution cycle?

(A) ALU performs the arithmetic & logical operation.

(B) Effective address is calculated.

(C) Next instruction is fetched.

(D) Branch address is calculated & Branching conditions are

checked.

Ans. (D)

Q.29 A circuit in which connections to both AND and OR arrays can be

programmed is called

(A) RAM (B) ROM

(C) PAL (D) PLA

Ans. (A)

Q.30 If a register containing data (11001100)2 is subjected to arithmetic shift left

operation, then the content of the register after 'ashl' shall be

(A) (11001100)2 (B) (1101100)2

(C) (10011001)2 (D) (10011000)2

Ans. (D)

Q.31 Which logic is known as universal logic?

(A) PAL logic. (B) NAND logic.

(C) MUX logic. (D) Decoder logic.

Ans. (B)

Q.32 The time for which the D-input of a D-FF must not change after the clock is

applied is known as

(A) Hold time. (B) Set-up time.

(C) Transition time. (D) Delay-time.

Ans. (A)

Q.33 How many memory chips of (128 x 8) are needed to provide a memory

capacity of 4096 x 16?

(A)64 (B) A B

(C)32 (D) None

Ans. (A)

Q.34 In addition of two signed numbers, represented in 2' s complement form

generates an overflow if

(A) A. B = 0 (B) A = 0

(C) A Å B = 1 (D) A + B = 1

Ans. (C)

Where A is the carry in to the sign bit position and B is the carry out of the

Sign bit position.

Q.35 Addition of (1111)2 to a 4 bit binary number 'a' results:-

(A) Incrementing A (B) Addition of (F)H

(C) No change (D) Decrementing A

Ans. (C)

Q.36 In a microprocessor system, suppose. TRAP, HOLD, RESET Pin

got activated at the same time, while the processor was executing some

instructions, then it will first respond to

(A) TRAP (B) HOLD

(C) RESET (D) None

Ans. (D)

Q.37 Pseudo instructions are

(A) Machine instructions (B) Logical instructions

(C) Micro instructions (D) instructions to assembler.

Ans. (A)

Q.38 An attempt to access a location not owned by a Program is called

(A) Bus conflict (B) Address fault

(C) Page fault (D) Operating system fault

Ans. (B)

Q. 39 Dynamic RAM consumes ________ Power and ________ then the Static RAM.

(A) more, faster (B) more, slower

(C) less, slower (D) less, faster

Ans. (C)

Q.40 The flag register content after execution of following program by 8085

microprocessor shall be

Program

SUB A

MVI B, (01)H

DCR B

HLT

(A) (54)H (B) (44)H

(C) (45)H (D) (55)H

Ans. (A)

Q.41 Which flag of the 8085's flag register is not accessible to programmer

directly?

(A)Zero flag

(B)Carry flag

(C)Auxiliary carry flag

(D)Parity flag

Ans. (C)

Q.42 Cache memory works on the principle of

(A) Locality of data.

(B) Locality of reference

(C) Locality of memory

(D) Locality of reference & memory

Ans. (B)

Q.43 Which of the following is a Pseudo instruction?

(A) SPHL (B) LXI

 (C) NOP (D) END

Ans. (D)

Q.44 A demultiplexer can be used as

(A)Encoder (B)Decoder

(C)Multiplexer (D)None of the above

Ans. (B)

Q.45 Excess-3 equivalent representation of (1234)H is

(A) (1237)Ex-3 (B) (4567)Ex-3

(C) (7993)Ex-3 (D) (4663)Ex-3

Ans. (B)

Q.46 Which of the memory holds the information when the Power Supply is switched

off?

(A) Static RAM (B) Dynamic RAM

(C) EEROM (D) None of the above

Ans. (C)

Q.47 Minimum no. of NAND gate required to implement a Ex-OR function is

(A)2 (B)3

(C)4 (D)5

Ans. (C)

Q.48 Which of the following interrupt is maskable?

(A)INTR (B)RST 7.5

(C)TRAP (D)Both (A) and (B)

Ans. (B)

Q.49 Which of the following expression is not equivalent to x?

(A) x NAND x (B) x NOR x

(C) x NAND 1 (D) x NOR 1

Ans. (D)

Q.50 Word 20 contains 40

Word 30 contains 50

Word 40 contains 60

Word 50 contains 70

Which of the following instructions does not, load 60 into the Accumulator

(A) Load immediate 60

(B) Load direct 30

(C) Load indirect 20

 (D) both (A) & (C)

Ans. (B)

Q.51 An interrupt for which hardware automatically transfers the program to a specific

memory location is known as

(A) Software interrupt

(B) Hardware interrupt

(C) Maskable interrupt

(D) Vector interrupt

Ans. (B)

Q.52 Synchronous means _______

(A) At irregular intervals

(B) At same time

(C) At variable time

(D) None of these

Ans. (B)

Q.53 'n' Flip flops will divide the clock frequency by a factor of

(A)n2 (B) n

(C)2n (D) log (n)

Ans. (B)

Q.54 In DMA the data transfer is controlled by

(A)Microprocessor (B) RAM

(C)Memory (D) I/O devices

Ans. (D)

Q.55 The number of instructions needed to add a numbers an store the result in memory

using only one address instruction is

(A)n (B) n - 1

(C)n +1 (D) Independent of n

Ans. (D)

Q.56 Negative numbers cannot be represented in

(A)Signed magnitude form

(B)I's complement form

(C)2's complement form

(D)8-4-2-1 code

Ans. (C)

Q.57 Which of the following architecture is/are not suitable for realizing SIMD

(A)Vector Processor (B) Array Processor

 (C)Von Neumann (D) All of the above

Ans. (C)

Q.58 In Boolean expression A+BC equals

(A)(A+B)(A+C) (B) (A'+B)(A'+C)

(C)(A+B)(A'+C) (D) (A+B)C

Ans. (A)

Q.59 A JK flip-flop can be implemented using D flip-flop connected such that

(A)D=JQ+KQ (B) D=JQ+KQ

(C)D=JQ+KQ (D) D=JQ+KQ

Ans. (A)

Q.60 An effective solution to the power consumption problem lies in using _______

transistors to implement ICs.

(A) NMOS (B) TTL shottky

(C) PMOS (D) both NMOS & PMOS

Ans. (D)

Q.61 Memory interleaving technique is used to address the memory modules in order to

have

(A) higher average utilization

(B) faster access to a block of data

(C) reduced complexity in mapping hardware

(D) both (A) & (B)

Ans. (C)

Q.62 In a multiprogramming system, which of the following is used

(A) Data parallelism (B) Paging concept

(C) L1 cache (D) None of the above

Ans. (B)

Q.63 Cycle stealing technique is used in

(A) Interrupt based data transfer

(B) Polled mode data transfer

(C) DMA based data transfer

(D) None of these

Ans. (C)

Q.64 Manipulation of individual bits of a word is often referred to as

(A) Bit twidding (B) Bit swapping

(C) Micro-operation (D) None of these

Ans. (A)

Q.65 Which of the following is not a characteristic of a RISC architecture.

(A) Large instruction set (B) One instruction per cycle

(C) Simple addressing modes (D) Register-to-register operation

Ans. (A)

Q.66 When CPU is not fully loaded, which of the following method of data transfer is

preferred

(A) DMA (B) Interrupt

(C) Polling (D) None of these

Ans. (D)

Q.67 Associative memory is some times called as

(A) Virtual memory (B) Cache memory

(C) Main memory (D) Content addressable memory

Ans. (D)

Q.68 BCD equivalent of Two's complement is

(A) nine's complement (B) ten's complement

(C) one's complement+1 (D) none of these

Ans. (C)

Q.69 PAL circuit consists of

(A) Fixed OR & programmable AND logic

(B) Programmable OR & Fixed AND Logic

(C) Fixed OR & fixed AND logic

(D) Programmable OR & programmable AND logic

Ans. (A)

Q.70 8085 microprocessor carryout the subtraction by

(A) BCD subtraction method

(B) Hexadecimal subtraction method

(C) 2’s complement method

(D) Floating Point subtraction method

Ans. (C)

Q.71 CPU checks for an interrupt signal during

(A) Starting of last Machine cycle

(B) Last T-State of instruction cycle

(C) First T-State of interrupt cycle

(D) Fetch cycle

Ans. (B)

Q.72 During DMA acknowledgement cycle, CPU relinquishes

(A) Address bus only (B) Address bus & control bus

(C) Control bus & data bus (D) Data bus & address bus

Ans. (D)

Q.73 If the clock input applied to a cascaded Mod-6 & Mod-4 counter is 48KHz. Than

the output of the cascaded arrangement shall be of

(A) 4.8 KHz (B) 12 KHz

(C) 2 KHz (D) 8 KHz

Ans.(C)

Q.74 If the stack pointer is initialised with (4FEB)H, then after execution of Push

operation in 8085 microprocessor, the Stack Pointer shall be

(A) 4FEA (B) 4FEC

(C) 4FE9 (D) 4FED

Ans. (D)

Q.75 A more efficient way to organise a Page Table is by means of an associative

memory having

(A) Number of words equal to number of pages

(B) Number of words more than the number of pages

(C) Number of words less than the number of pages

(D) Any of the above

Ans. (A)

Q.76 If there are four ROM ICs of 8K and two RAM ICs of 4K words, than the address

range of Ist RAM is (Assume initial addresses correspond to ROMs)

(A) (8000)H to (9FFF)H (B) (6000)H to (7FFF)H

(C) (8000)H to (8FFF)H (D) (9000)H to (9FFF)H

Ans. (C)

Q.77 AÅBÅC is equal to A B C for

(A) A=0, B=1, C=0 (B) A=1, B=0, C=1

(C) A=1, B=1, C=1 (D) All of the above

Ans. (D)

Q.78 Gray code equivalent of (1000)2 is

(A) (1111)G (B) (1100)G

(C) (1000)G (D) None of these

Ans. (A)