Intel 8086 Microprocessor Architecture
Introduction
The 8086 was the first 16-bit Microprocessor to be introduced by
Intel Corporation. The word 16-bit means that its arithmetic logical unit,
internal registers, and most of its instructions are designed to work with
16-bit binary words. The 8086 has a 16-bit data bus, so it can read data form
or write data to memory and ports either 16-bits or 8- bits at a time. The 8086
has a 20-bit address bus, so it can address any one of 220 or 1,048,576 memory
locations. Each of the 1,048,576 memory addresses of the 8086 represents a
byte-wide location. Words will be stored in two consecutive memory locations.
If the first byte of a word is at an even address, the 8086 can read the entire
word in one operation. If the first byte of the word is at an odd address, the
8086 will read the first byte of the word in one operation, and the second byte
in another operation.
Features:
·
Released by Intel in 1978
·
Produced from 1978 to 1990s
·
A 16-bit microprocessor chip.
·
Max. CPU clock rate:5 MHz to 10 MHz
·
Instruction set: x86-16
·
Package: 40 pin DIP
·
16-bit Arithmetic Logic Unit
·
16-bit data bus (8088 has 8-bit
data bus)
·
20-bit address bus - 220 = 1,048,576 = 1 meg
·
The address refers to a byte in memory.
·
In the 8088, these bytes come in
on the 8-bit data bus. In the 8086,
bytes at even addresses come in on the low half of the data bus (bits 0-7) and bytes
at odd addresses come in on the upper
half of the data bus (bits 8-15).
·
The 8086 can read a 16-bit word at an even address in one operation and
at an odd address in two operations. The
8088 needs two operations in either case.
·
The least significant byte of a word on an 8086 family microprocessor is
at the lower address.
The 8086 microprocessor
architecture is internally divided into two separate functional units.
·
Bus Interface
Unit (BIU)
·
Execution
Unit (EU).
(REFER DIAGRAM 1-Figure
shows a block diagram of the 8086 internal architecture.)
The BIU fetches
instructions, reads data from memory and ports, and writes data to memory and
I/O ports. The EU executes instructions that have already been fetched by the
BIU. The BIU and EU function independently. The BIU interfaces the 8086 to the
outside world. The BIU provides all external bus operations. The BIU contains
segment registers, instruction pointer, instruction queue, and address
generation bus control circuitry to provide functions such as fetching and
queuing of instructions, and bus control.
The BIU’s instruction queue is a First-In First-out
(FIFO) group of registers in which up to six bytes of instruction code are
perfected from memory ahead of time. This is done in order to speed up program
execution by overlapping instruction fetch with execution. This mechanism is
known as pipelining. If the queue is full and the EU does not request BIU to
access memory, the BIU does not perform any bus cycle. On the other hand, if
the BIU’s is not full and if it can store at least two bytes and the EU does
not request it to access memory, the BIU may prefect instructions. However, if
BIU is interrupted by EU for memory access while the BIU is in the process of
fetching an instruction, the BIU first completes fetching and then services the
EU : the queue allows the BIU to keep the EU supplied with perfected
instructions without typing up the system bus. If an instruction such as Jump
or subroutine call is encountered, the BIU will reset the queue and begin
refilling after passing the new instruction to the EU.
The
BIU contains a dedicated adder, which is used to produce the 20-bit address.
The bus control logic of the BIU generates all the bus control signals such as
read and write signals for memory and I/O.
The
BIU has four 16-bit segment registers. These are the Code Segment (CS)
register, the Data Segment (DS) register, the Stack Segment (SS) register, and
the Extra Segment (ES) register. The 8086’s one-megabyte memory is divided into
segments of up to 64K bytes each. The 8086 can directly address four segments
(256K byte within the 1 Mbytes memory) at a particular time. Programs obtain
access to code and data in the segments by changing the segment register
contents to point to the desired segments. All program instructions must be
located in main memory pointed to by the 16-bit CS register with a 16-bit
offset in the segment contained in the 16-bit instruction pointer (IP). The BIU
computes the 20-bit physical address internally using the programmer-provided
logical address (16-bit contents of CS and IP) by logically shifting the
contents of CS four bits to left and then adding the 16-bit contents of IP. In
other words, the CS is multiplied by 1610 by the BIU for computing
the 20-bit physical address. This means that all instructions of a program are
relative to the contents of the CS register multiplied by 16 and then offset is
added provided by the 16-bit contents of IP. For example, if [CS] = 456A16
and [IP] = 162016, then the 10-bit physical address is generated by
the BIU as follows:
Four times logically shifted [CS] to left =
456A016
+ [IP] as offset =
162016
20-bit physical address =
46CC016
The
BIU always inserts four Zeros for the lowest 4-bits of the 20-bit starting
address (physical) of a segment. In the other words, the CS contains the base
or start of the current code segment, and IP contains the distance or offset
from this address to the next instruction byte to be fetched. Note that
immediate data are considered as part of the code segment.
The
SS register points to the current stack. The 20-bit physical stack address is
calculated from SS and SP for stack instruction such as PUSH and POP. The
programmer
Can use the BP register instead of SP for accessing
the stack using the based addressing mode. In this case, the 20-bit physical
stack address is calculated from BP and SS.
The
DS register points to the current data segment; operands for most instructions
are fetched from this segment. The 16-bit contents of Source Index (SI) or
Destination Index (DI) are used as offset for computing the 20-bit physical
address.
The
ES register points to the extra segment in which data (in excess of 64k pointed
to by DS) is stored. String instructions always use ES and DI to determine the
20-bit physical address for the destination.
The
segment can be continuous, partially overlapped, fully overlapped, or disjoint.
An example of how five (segment 1 through segment 5) may be stored in physical
memory are shown.
a)Segments are contiguous (adjacent)
a)Segments are contiguous (adjacent)
SEGMENTS 1 an d 2 are partially
overlapped, SEGMENTS 2 and 3 are fully overlapped, and SEGMENTS 2 and 4 are
disjoint.. Every segment must start on 16-byte memory boundaries.
Typical
examples of values of segments should then be selected based on physical
addresses starting at 0000016 , 0001016 , 0002016 , 0003016, … FFFF016 . A physical memory location may be
mapped into (contained in) one or more logical segments. Many applications can
be written to simply initialize the segment and then forget them.
When the processor obtains a logical address (segment and offset), it performs a simple calculation to determine the 20-bit physical address in memory to which the logical address refers:
physical address = (segment << 4) + offsetThis is equivalent to multiplying the segment by 16 and adding the offset (i.e., physical address = segment * 16 + offset). This means that the 64 KB segments overlap, with a new segment starting every 16 bytes. This also means that there can be more than one address for the same memory location. For example, 0000:0100, 0001:00F0, and 0010:0000 all refer to physical address 0x100
The EU decodes and executes instructions. A decoder
in the EU control system translates instructions. The EU has a 16-bit ALU for
performing arithmetic and logic operations.
The
EU has eight 16-bit general registers. These are AX, BX, CX, DX, SP, BP, SI,
and DI. The 16-bit registers AX, BX, CS, and DX can be used as two 8-bit
registers (AH, AL, BH, BL, CH, CL, DH, DL). For example, the 16-bit register DX
can be considered as two 8-bit registers DH (high byte of DX) and DL (low byte
of DX). The general-purpose registers AX, BX, CX, and DX are named after
special functions carried out by each one of them. For example, the AX is called
the 16-bit accumulator while the AL is the 8-bit accumulator. The use of
accumulator registers is assumed by some instructions. The Input/Output (IN or
OUT) instructions always use AX or AL for inputting/outputting 16- or 8-bit
data to or from and I/O port.
Multiplication
and division instructions also use AX or AL. The AL register is the same as the
8085 A register.
BX register is called the base register. This is
the only general-purpose register, the contents of which can be used for
addressing 8086 memory. All memory references utilizing these register contents
for addressing use Ds as the default segment register. The BX register is
similar to 8085 HL register. In other words, 8086 BH and BL are equivalent to
8085 H and L registers, respectively.
The CX register is known
as the counter register. This is because some instructions such as shift
rotate, and loop instructions use the contents of CX as a counter. For example,
the instruction LOOP START will automatically decrement CX by 1 without
affecting flags and will check if [CX]=0. If is zero, the 8086 executes the
next instruction; otherwise the 8086 branches to the label START.
The data register DX is
used to hold high 16-bit result (data) in 16* 16 multiplication or high 16-bit
dividend (data) before a 32 ¸16 division and the 16-bit remainder after the
division.
The two pointer registers,
SP (stack pointer) and BP (base pointer), are used to access data in stack
segment. The SP is used as an offset from the current SS during execution of
instructions that involve stack segment in external memory. The SP contents are
automatically updated (incremented or decremented) due to execution of POP or
PUSH instruction.
The base pointer contains
an offset address in the current SS. This offset is used by the instructions
utilizing the based addressing mode.
The FLAG
register in the EU holds the status flags typically after an ALU operation.
The 8086 have
six one-bit flags. AF (Auxiliary carry flag) is used by BCD bit) into the high
nibble or a borrow from the high nibble into the low nibble of the low-order
8-bit of a 16-bit number. CF (Carry Flag) is set if there is a carry from
addition or borrow from subtraction. OF (Overflow Flag) is set if there is an
arithmetic overflow, that is, if the size of the result exceeds the capacity of
the destination location. An interrupt on overflow instructions is available
which will generate an interrupt in this situation. SF (Sign Flag) is set if
the most significant bit of the result is one (Negative) and is cleared to zero
for non-negative result. PF (Parity Flag) is set if the result has even parity;
PF is zero for odd parity of the result. ZF (Zero Flag) is set if the result is
zero; ZF is zero for non-zero result.
The 8086 has three control
bits in the flag register which can be set or reset by the programmer: setting
DF (Direction Flag) to one causes string instructions to auto decrement and clearing
DF to zero causes string instructions to auto increment. Setting IF (Interrupt
Flag) to one causes the 8086 to recognize external mask able interrupts;
clearing IF to zero disables these interrupts. Setting TF (Trace Flag) to one
places the 8086 in the single-step mode. In this mode, the 8086 generate an
internal interrupt after execution of each instruction. The user can write a
service routine at the interrupt address vector to display the desired
registers and memory locations. The user can thus debug a program
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