Intel 8086 Microprocessor PINS and SIGNALS Description

            The 8086 pins and signals are shown below.  Unless otherwise indicated, all 8086 pins are TTL compatible.  The 8086 can operate in two modes.  These are minimum mode (uniprocessor system – single 8086) and maximum mode (multiprocessor system system – more than one 8086).   Pin Diagram for the 8086  is given below:

Pin(s)	Symbol	Input/ Output	Description
1	GND	-	Ground
2-16	AD14-ADO	I/O-3	Address lines A0-A15 and Data lines D0-D15 are multiplexed in 8086. These lines are labelled as AD0-AD15, Output address during the first part of the bus cycle and inputs or outputs data during the remaining part of the bus cycle.
17	NMI	I	Nonmaskable interrupt request level triggered
18	INTR	I	Maskable interrupt request level triggered
19	CLK	I	Generates clock signals that synchronize the operation of processor.
20	GND		Ground
21	RESET	I	Terminates activity, clears PSW, IP, DS,SS,ES, and the instruction queue, and sets CS to FFFF; IP to 0000H; SS to 0000H; DS to 0000H; PSW to 0000H.  Processing begins at FFFFO when signal is dropped. Signal must be 1 for at least 4 clock cycles.
22	READY	I	Acknowledgment from memory or I/O interface that cpu can complete the current bus cucle.
23	TEST	I	Used in conjuction with the WAIT instruction in multiprocessing environments.  A WAIT instruction will cause the cpu to idle, except for processing interruptsm, until a 0 is applied to this pin see chp-11
24-31			Definition depends on mode
32	RD	0-3	Indicates a memory or I/O read is to be performed
33	MN/MX	I	Cpu is in minimum mode when strapped to +5 v and in maximum mode when grounded
34	BHE/s7	0-3	If o during first of bus cycle this pin indicates that at least one byte of the current transfer is to be made on pins AD15-AD8 if 1 the transfer is made on AD7-AD0. Status s7 is output during the latter part of bus assigned a meaning
35-38	A19/s6- A16/s3	0-3	During the first part of the bus cycle the upper 4 bits of the address are output and during the remainder of the bus cycle status is output. S3 and S4 indicates the segment register being used as follows; S4 s3 Register       0    0   ES       0    1   SS 1        0  CS or more 1    1  DS s5 gives the current setting of IF. S6 is always 0.
39	AD15	I/0-3	Same as AD14-AD0
40	Vcc		Supply voltage - +5 v ± 10%

MN/MX is an input pin used to select one of these modes.  When MN/MX is HIGH, the 8086 operates in the minimum mode.  When MN/MX is LOW, 8086 is configured to support multiprocessor systems.  8086 microprocessors can be configured to work in either of the two modes: the minimum mode and the maximum mode

ü      Minimum mode:

Ø      Pull MN/MX to logic 1

Ø      Typically smaller systems and contains a single microprocessor

Ø      Cheaper since all control signals for memory and I/O are generated by the microprocessor.

ü      Maximum mode

Ø      Pull MN/MX logic 0

Ø      Larger systems with more than one processor (designed to be used when a coprocessor (8087) exists in the system)

1. Pins 2 through 16 and 39 (AD15 - AD0) are a 16-bit multiplexed address/data bus.  During the first clock cycle AD0-AD15 are the low order 16 bits of address.  The 8086 have a total of 20 address lines.  The upper four lines (35 – 38)are multiplexed with the status signals for the 8086.  These are the A16/S3, A17/S4, A18/S5, and A19/S6.  During the first clock period of a bus cycle, the entire 20-bit address is available on these lines.  During all other clock cycles for memory and I/O operations, AD15-AD0 contains the 16-bit data, and S3, S4, S5, and S6 become status lines.  S3 and S4 lines are decoded as follows:

A17/S4           A16/S3           Function

0                      0                      Extra segment

0                      1                      Stack segment

1                      0                      Code or no segment

1                      1                      Data Segment

Status bits S3 and S4 indicate the segment register that is being used to generate the address the address and bit S5 reflects the contents of the IF flag.  S6 is always held at 0 and indicates that an 8086 is controlling the system bus.

2. Pins 1 and 20 are grounded.  Pin 17 is NMI. This is the Non Maskable Interrupt input activated by a leading edge.  Pin 18 is INTR.  INTR is the maskable interrupt input.  Pin 19 is CLK is for supplying the clock signal that synchronizes the activity within the CPU.
3. Pin 21 (RESET) is the system reset input signal.  When the 8086 detects the positive going edge of a pulse on RESET, it stops all activities until the signal goes LOW.  When the reset is low, the 8086 initializes as follows:

8086 Component    Content

Falgs                          Clear

IP                                 0000H

CS                              FFFFH

DS                              0000H

SS                               0000H

ES                               0000H

Queue             Empty

4. Pin 22 (READY) is for inputting an acknowledge from a memory or I/O interface that input data will be put on the data bus or output data will be accepted from the data bus within the next clock cycle.  In either case, the CPU and its bus control logic can complete the current bus cycle after the next clock cycle.
5. Pin 23 TEST is an input pin and is only used by the WAIT instruction.  The 8086 enter a wait state after execution of the WAIT instruction until a LOW is seen on the TEST pin.
6. Pins 24 to 31 are mode dependent and are considered later.
7. Pin 32 (RD) is LOW whenever the 8086 is reading data from memory or an I/O location.
8. Pin 34 (BHE/S7) is used as BHE (BUS High Enable) during the first clock cycle of an instruction execution.  BHE can be used in conjunction with AD0 to select memory banks.  During all other clock cycles BHE/S7 is used as S7.

Operation                                           BHE    AD0                Data pins used

Write/Read a word at an even

Address                                             0          0                      AD15 – AD0

Write/Read a byte at an even

Address                                             1          0                      AD7 – AD0

Write/Read a byte at an odd

Address                                             0          1                      AD15 – AD8

Write/Read a word at an odd

Address                                             0          1                      AD15 – AD8

                                                            1         0                       AD7 - AD0

9. Pin 40 (VCC) receives the supply voltage, which must be +5 V.